Katie Dropiewski

-Developed and optimized a simplified scan chain macro for use in early yield learning -Designed clock tree generation flow using Cadence automatic place and route tool -Identified and modelled path to analyze Cadence results with Hpice simulations -Presented conclusions regularly using posters and PowerPoint slide decks

-Researching, fabricating and characterizing transistors made out of novel materials, such as GaSb and InAs, in atypical structures, including nanowires and fins. -Building the gate and source/drain portion of the stack using a variety of manufacting tools. -Operating deposition tools that use different mechanisms to coat a surface with material, including Magnetron Sputtering (PVD), Atomic Layer Deposition (ALD) and E-beam Evaporation. -Operating contact alignment photolithography tools, chemical and plasma etches (RIE) to remove unwanted material in conjunction with photolithography. -Optimizing manufacturing processes for nanowires to improve their potential as the channel for field-effect transistors as well as built the gate and source/drain contacts of the device stack for field-effect transistors (FET) using fins as the channel. -Analyzing FETs using a broad range of optical, physical and electrical characterization techniques, including optical microscopy, Scanning Electron Microscopy (SEM), Elastic backscattering spectrometry (EBS), Capacitance-Voltage profiling, two-point probing, four-point probing, and Current-voltage profiling. -Presenting data regarding her research in poster and lecture format.

-Developed and executed test plan for DDR Memory Signal Integrity Validation -Collaborated with HIP Design Engineers, Memory Reference Code Engineers to improve yield -Identified bugs caused by semiconductor variation on SoC products -Developed complete automation software for voltage and temperature permutations on SoC products -Resolved FPGA bugs in collaboration with tool owner -Identified and root-caused RTL and Firmware bugs via Veloce emulation environment -Identified and debugged multiple electrical and logical failures on silicon -Developed and executed test content in SLE and FPGA emulation systems -Designed and owned test plans for multiple IPs for pre- and post-silicon -Trained and managed contractor resources as technical expert