Weichun Xu
Member of The Honor Society of Phi Kappa Phi
From Shanghai, Shanghai
From Shanghai, Shanghai
7 year in ASIC/SoC Verification.
Familiar with Perl/Python/Shell and able to write simple Tcl and Makefile.
Familiar with SystemVerilog, VMM and UVM.
Working areas include I2C/SPI, Ethernet and Coresight.
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Weichun Xu Inducted into The Honor Society of Phi Kappa Phi
Weichun Xu of Melbourne, Fla., was recently initiated into The Honor Society of Phi Kappa Phi, the nation's oldest and most selective collegiate honor society for all academic disciplines. Xu was ...
May, 07 2015 - Verified by The Honor Society of Phi Kappa Phi
SoC Verification Engineer at NVIDIA Corp. (NVDA)
1. Verified ARM based mobile chips
• System level verification of Debug Modules (Coresight/DDS/DP2) for ARM A15 mobile chip using assembly/C++
• System level verification of Coresight/AHB Bus/APB Bus/Apbdma for ARM V8 mobile chip using C++
• Formal verification of OBS connection in system level for ARM A9/A15 mobile chips using IFV/Jasper and TCL
• Created the formal verification flow of OBS connection using Perl
• Formal verification of fuse connection in system level for ARM V8 mobile chip using Jasper and TCL
• Wrote the test plans using Python
November 2011 - December 2013
Digital IC Design and Verification Engineer at Lattice Semiconductor Corp. (LSCC)
1. Worked on a CPLD chip
• Collected code coverage of some interface modules using Cadence IUS
• Wrote the simulation model of a module
2. Verified an FPGA chip
• Block & system level verification of DSP (DSP is schematic-based) using Cadence IUS
May 2010 - December 2011
Verification Engineer at Huawei Technologies Company Ltd.
1. Worked on an AP chip
• Unit level, integration level and post-sim level verification of Ethernet (MII) using VCS and VMM
• Used Synopsys AHB VIP and Ethernet VIP in building the verification environment
• Used VMM scenario to write constrained random tests
• Wrote the Perl script to extract the log and compare the result for integration level and post-sim level verification
2. Verified a Multi-core wireless network chip
• Established the integration level verification environment (without CPU) using VCS/VMM and AXI VIP
• Wrote the Perl script to generate constrained random tests based on VMM for AXI bus connection
• Integrated the unit level verification environment of Ethernet (GMII)/SPI into integration level
• Unit level and integration level verification of Ethernet (GMII) using VCS/VMM and AHB/Ethernet VIP
• Wrote VMM random constrained tests for unit level and integration level verification of Ethernet
• Integration level verification of SPI
3. Worked on a Multi-core wireless network chip
• Generated emulation version (Mentor Graphics Veloce, ICE mode) using Makefile and Shell
4. Support & Training
• Provided technical support to colleagues in using Hisilicon’s UT verification platform
• Conducted the training schedule of the department
• Trained team members on SVTB/VMM
April 2008 - May 2010
