Gaurav Ahuja

Seeking an full time position in VLSI circuit design from Jan 2016, which involve designing circuits, simulating for timing, power, speed. Currently : Pursuing M.S Electrical and Computer Engineering at ( Georgia Institute of Technology, Atlanta, Georgia ) Relevant Industry Experience : 2 years & 8 months. Skills: Tools (Adept) : Cadence Virtuoso, ADE, Cdesigner, Modelsim, nWave, Ezwave, Wave Viewer, Xelga. Simulators (Adept) : Hspice, Eldo Spice, Xa, Hsim. Languages (Adept) : Verilog, Shell Scripting, TCL, C Others ( Familiar) : Soc Encounter, C++, Matlab. Experience: Design validation and timing verification of Digital and Analog circuits. SRAM/Register File architectures and advanced full custom circuit implementations. Direct experience with advanced Nanotechnology nodes : 55nm, 40nm, 32nm, 28nm, 20nm. Hands on work with FINFET devices - 16nm & 14nm. Characterization and generation of timing files for SRAMs. Schematic entry, simulation of major blocks, layout planning and interface with CAD team for full verification and model generation. Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. Experience in writing Spice stimulus, measurement files. Familiarity with variation-aware design in nanometer technology nodes, statistical analysis. Experience with RTL coding in Verilog for functional verification. Good Business sense and market- aware product development. Good communications and presentation skills.