Pallavi Kinnera

Pursuing Masters in Electrical and Computer Engineering, with specialization in VLSI and Computer Architecture, at the Georgia Institute of Technology Currently, working as RLS CAD DTS Intern at Intel Corporation. My primary role is automation of physical design from RTL using EDA vendor and in-house design automation tools, validating results, ensuring circuit performance and satisfying the layout rules. EXPERTISE: Digital Logic Design, Low power implementation, Design of Memory Systems Circuit Modelling, LVS, Logic Simulation, Circuit Simulation, RTL Designing DFT, Fault Modelling ,Fault Simulation Distributed programming with MPI ,Parallel programming with pthreads Graphics programming using OpenGL, Using non-blocking system I/O Ability to create and execute effective presentations to a wide variety of audience. Experienced in writing both academic and industrial technical reports. Written journal and conference paper. SKILLS: Hardware Description Language: Verilog, VHDL EDA Tools: Cadence Virtuoso, H-Spice, Cadence Encounter Digital Implementation, PSpice Tensilica/Xtensa SDK Toolkit, Keil Embedded C Cleanroom: Accustomed to cleanroom procedures for IC Fabrication