Prasanna Srinivasan

• Developed standard and re-usable mappings and Mapplets using various transformations like Joiner, Aggregator, Update Strategy, Rank, Router, Lookup - Connected & Unconnected, Sequence Generator, Filter, Sorter, Source Qualifier, Stored Procedure transformation etc. • Wrote UNIX Shell Scripts to run database jobs on server side. • Developed new and modified existing packages, Database triggers, stored procedure and other code modules using PL/SQL in support of business requirements. • Worked with various functional experts to implement their functional knowledge into business rules in turn as working code modules like procedures and functions. • Involved in daily, weekly and monthly load of data from mainframe data set to Oracle database. • Used SQL *Loader to load the data. • Generated UNIX shell scripts for automating daily load processes. • Developed Pre and Post SQL scripts, PL/SQL stored procedures and functions. • Developed Shell Scripts, PL/SQL procedures, for creating/dropping of table and indexes of performance for pre and post session management. • Used TOAD and SQL navigator extensively.

• Verified the Signal Integrity of the digital board used in their products using Cadence PCB tool • Electrical Constrain sets are created in SigXplorer and are applied to the design using constraint manager • Assigning IBIS model for the IC’s used in the board • The digital signals are manually measured and compared with the simulated result to verify the integrity of the signals under review • Reflection problem was found in a net and was solved using termination strategies such as source and load termination. • Performed circuit analysis, timing analysis, noise/EMI analysis, reliability analysis and Signal Integrity simulation, using HSPICE, Cadence PCB SI, and self-coded scripts. Traded off risk, feature, performance and schedule • Developed validation testing procedure and instruction; used Tektronix Real-Time and Sampling oscilloscope to validate spec compliance; debugged failures

• Wrote behavioral and RTL models and testbenches in Verilog and SystemVerilog using OVM • Performed AMS verification for the models developed in Verilog and System Verilog using Cadence tools • Ran and wrote some Perl and Shell scripts for top level regression test for the Design Under Test and verified the same using Simvision • Wrote Assertions in Verilog and SystemVerilog to monitor the functionality of the Design Under Test. • Created Makefile with contains all the test cases to be applied for the Design Under Test.