Suma George

Bio-inspired Classifier for Speech Recognition in 350nm CMOS IC • Demonstrated first classifier structure using bio-inspired CMOS dendrites (BIOCAS 2011). • YES/NO wordspotter built using dendrite inspired circuit model and Winner-Take-All circuits. This can be used as a backend for a front-end filterbank and feature extraction stage. First Neuromorphic FPAA SoC (350nm CMOS) • Co-architect of first Neuromorphic SoC FPAA. • Developed an integrated IC with analog, digital and neuron CAB (Computational Analog Blocks) and an on-chip processor, DAC/ADC and peripherals. • Design and layout for neuron circuit models. • Design and layout for digital and analog peripheral circuits for the chip. First Integrated FPAA SoC (350nm CMOS) • Key member of the design team to build new FPAA SoC called RASP. 3.0. Top-level architect: Prof. Hasler • Detailed digital simulations of MSP430 processor for RASP 3.0. • Designed and implemented a memory controller for RASP 3.0. • Layout design for different peripheral blocks of the chip. • Testing the chip for applications in speech processing and image processing • Building the tool framework for this chip. • Design and verification of digital infrastructure which uses an open-core processor. First RF FPAA SoC (40nm CMOS) • Design and layout of 8T SRAM unit for the IC. • Design and layout for peripheral blocks, digital blocks and processor of this IC. Integrated Hardware-Software CoDesign for Heterogeneous ICs • Developed software tool infrastructure for FPAAs. • Integrated tool flow allows digital and analog co-design. Demonstrated various mixed-signal design using this novel approach. • All tools are built on an open-source platform. Co-instructor, Neuromorphic Analog VLSI- ECE 6435 • Co-taught graduate level course in Spring 2014. • Organized labs and lectures.