Suman Ghosh

Electrical and Computer Engineering PhD student with a strong grasp over core skills like Digital Design and Digital Signal Processing. Well-versed in Verilog and SystemVerilog. Experienced in using scripting languages like Python and Perl. Fundamental knowledge about C/C++. Hands-on experience with Cadence Virtuoso, LTSpice, ModelSim, Vivado, MATLAB, and SIMULINK. I have a clear fundamental idea about verification and testing methodologies used in the VLSI industry. Currently working as a Research Assistant on Electromigration in Interconnect networks using hydrostatic stress simulation (Korhonen's model) and modeling for multidimensional interconnect geometries using MATLAB and COMSOL. Also, developing MARS models for wire-sizing and calibration in complex interconnect networks. I find Digital Signal Processing, RTL design and verification, data analytics, and statistical modeling to be very interesting and I am willing to work in the VLSI industry to learn and gain experience on my existing skills and also develop new skills. My foremost aim is to contribute as much as possible to the field I am working in as well as the organization I am working for. When I'm not busy with the serious stuff, you can catch me goofing in a fierce battle of wits with a Sudoku puzzle, trying to outsmart those sneaky numbers. And if I'm not getting tangled up in Sudoku's numerical enigma, I'm probably twisting my brain into a pretzel with a Rubik's cube, determined to conquer its colorful chaos. Life's too short not to enjoy the puzzling pleasures, right? Bring on the challenges!